System and method for fast re-locking of a phase locked loop circuit
US7714625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2008 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jan 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.