Double-triggered logic circuit
US7714627B1 · kind B1 · utility
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Key dates
| Filing date | Nov 21, 2008 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Nov 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate an adjustable pulse mode to solve the problem of threshold voltage loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.