Method and apparatus for synchronizing a clock generator in the presence of jittery clock sources
US7714631B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2005 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Oct 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided, in a clock generator for generating a plurality of output clock signals, an apparatus and method for synchronizing the clock generator to an input reference clock in the presence of a jittery input clock provided to the clock generator from a PLL. The clock generator and the PLL each have a divider with the same ratio. The apparatus includes a synchronizer (205) and a state machine (210). The synchronizer receives the input reference clock and the jittery input clock, and generates there from a synchronized input clock signal with respect to the jittery input clock. The state machine receives the synchronized input clock signal and the jittery input clock, synchronizes with the synchronized input clock signal using the jittery input clock, and abstains from a re-synchronizing operation when the jittery input clock has a jitter of up to a pre-defined maximum number of clock widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.