All digital Class-D modulator and its saturation protection techniques
US7714675B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Sep 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/217
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for modulating an input electrical signal are disclosed and may comprise modulating input signals utilizing a digital Class-D modulator and generating a digital output signal that is proportional to the input signals. The digital Class-D modulator may be comprised of four stages. To avoid integrator saturation, the output of at least one integrator stage may be limited by utilizing limiters in integrator feedback loops. The digital Class-D modulator utilizes a pulse width modulation technique. For increased signal to noise ratio (SNR) at a desired output power, the magnitude of a triangular waveform oscillator voltage may be greater than the magnitude of an integrated input signal. The digital output signal may be fed back to an input of at least one of the four stages in the digital Class-D modulator. The triangular waveform oscillator frequency may be adjusted to match desired output frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.