Delta-sigma PLL using fractional divider from a multiphase ring oscillator
US7715143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Nov 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2516
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A disk drive controller includes a servo system operable to associate a time stamp with an arrival of a servo wedge, a firmware loop and core PLLs in the read channel. The firmware loop is operable to determine a period between the arrival of a pair of consecutive servo wedges and produce a desired frequency of when to read/write data to disk based on the period between the arrival of a pair of consecutive servo wedges. Processing circuitry is operable to adjust a clock signal, wherein the clock signal itself is not locked to the data and produce a fine control signal for the core PLLs in the read channel. These core PLLs are operable to determine a phase and/or frequency associated with when an analog signal is sampled and/or written to disk, wherein these core PLLs comprises Fractional N Sigma Delta PLLs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.