Memory detecting circuit
US7715266B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 1, 2008 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Nov 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory detecting circuit includes five switch elements and two indication devices. A first switch element is connected to a standby power, and also connected to memory sockets of a first channel to receive a first memory detecting signal. A second switch element is connected to the first switch element and the standby power. A third switch element is connected to the second switch element and the standby power, and also connected to memory sockets of a second channel to receive a second memory detecting signal. A fourth switch element is connected to the third switch element and the standby power. A fifth switch element is connected to the fourth switch element and the standby power. When there are memories installed into the memory sockets of the first channel and the second channel, the second indication device indicates that the memories run in a dual channel mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.