Apparatus and method for matrix memory switching element
US7715377B2 · kind B2 · utility
15Cited by
10References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 19, 2005 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Feb 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.