Equalizer architecture for data communication
US7715472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Nov 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0055
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An update algorithm for equalizer coefficients in a communications system using phase correction symbols. Instead of using a traditional all symbols slicer update algorithm, the equalizer is updated during phase correction symbols for optimal performance in low signal-to-noise ratio conditions. In lower signal-to-noise ratio conditions, the equalizer uses a phase correction circuit to compensate for distortion caused by a communication channel when a demodulated data stream contains an unknown phase offsets resulting from a fast dynamic distortion. More specifically, the phase correction circuit uses a phase correction signal to correct for the unknown phase offsets in a demodulated data stream in lower signal-to-noise ratio conditions. The equalizer then corrects for distortion caused by the communication channel based upon the phase corrected demodulated data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.