Data synchronization apparatus
US7715513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jan 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/1446
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO buffer receives and stores a plurality of data and provides a FIFO adjustment signal according to the number of the data stored in the FIFO buffer. The data stored in the FIFO buffer are sent out to an external device at a clock rate derived from a master clock signal. The control circuit provides a PLL adjustment signal according to the FIFO adjustment signal. The PLL provides the master clock signal and adjusts the frequency of the master clock signal in response to the PLL adjustment signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.