High immunity clock regeneration over optically isolated channel
US7715726B2 · kind B2 · utility
5Cited by
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14Claims
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Key dates
| Filing date | May 21, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jul 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An optically isolated circuit device includes a first opto-isolator circuit that is driven by a first clock signal, and the output of the first opto-isolator circuit is used to drive a phase-locked loop (PLL) that is configured to synthesize a second clock signal having a frequency that is a multiple of the first clock signal frequency. The second clock signal is used as an input to a suitable clocked circuit of a type that benefits from optical isolation, such as an analog-to-digital converter (ADC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.