Erasure coding and group computations using rooted binary and ternary trees
US7716250B1 · kind B1 · utility
5Cited by
18References
11Claims
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Key dates
| Filing date | May 27, 2005 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jun 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/9027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
High throughput in data computations and processing is maintained while minimizing latency. A binary tree architecture is provided in which two trees are used simultaneously, and initiation of the trees is staggered to allow for optimal use of bandwidth. These techniques are desirable for erasure codes and other computations where the addition operator is commutative. Additionally, a ternary tree architecture may be used, in which three trees co-exist on the same set of nodes to maintain high throughput while further improving latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.