Method and system for performing parallel integer multiply accumulate operations on packed data
US7716269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jan 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.