Pseudo-full duplex communication using a half duplex communication protocol
US7716404B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2008 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | May 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1867
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a communication system having a master-slave arrangement communicating with each other using the RS485 protocol, an FPGA with a buffer memory is provided in the master and slave, respectively, to handle the actual communication. The CPUs of the master and slave transfer data to and from the respective buffer memory. The master's FPGA initiates and maintains communication with the slave's FPGA. The masters FPGA and the slave's FPGA communicate with each other using the RS485 protocol by transmitting requests, acknowledgements and data. From the standpoint of the CPUs of the master and slave, the communication appears to be full duplex, although the actual communication between the FPGAs is half duplex. One particular application of the communication method is a KVM switch system where the KVM switch acts as the master and the computers connected to the KVM switch act as slaves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.