Interfacing processors with external memory supporting burst mode
US7716442B2 · kind B2 · utility
2Cited by
8References
10Claims
0Family size
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Key dates
| Filing date | Sep 17, 2002 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple data devices (A,B,C) are interfaced via a bus arbiter (S) with an external memory (F) so as to support burst-mode access by each device (A,B,C) one or more read registers (R1,R2,R3) are provided in the memory (F), and each register (R1,R2,R3) supports burst-mode access by a corresponding device (A,B,C). The arbiter (s) selects the register to be used following the initial access burst, according to the device requiring access. Thus, the memory (F) supports multiple burst-mode accesses in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.