Patent · US Active

Reduced processing in high-speed reed-solomon decoding

US7716562B1 · kind B1 · utility

7Cited by

12References

20Claims

0Family size

Assignee

Link—A—Media Devices Corporation · US

Inventors

Yingquan Wu · Palo Alto, US
Meng Kun Lee · Cupertino, US
Kwok Alfred Yeung · Milpitas, US

Key dates

Filing date	Oct 18, 2005
Grant date	May 11, 2010
Priority date	—
Expiry date	Oct 1, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/6561
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is progressively removed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.