Method of circuit optimization utilizing programmable sleep transistors
US7716609B1 · kind B1 · utility
19Cited by
1References
17Claims
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Key dates
| Filing date | Oct 26, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimizing a circuit by calculating at least one parameter of a circuit based on a first size of at least one sleep transistor, calculating at least one parameter of the logic circuit based on a second size of the at least one sleep transistor. This process may be repeated for different sizes of the at least one sleep transistor to determine an optimum size of the at least one sleep transistor to optimize at least one parameter of the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.