Patent · US Active

Method for classifying errors in the layout of a semiconductor circuit

US7716613B2 · kind B2 · utility

1Cited by

9References

18Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Dirk Meyer · Frankfurt, DE
Thomas Harold Roessler · Menasha, US

Key dates

Filing date	Mar 1, 2007
Grant date	May 11, 2010
Priority date	—
Expiry date	Jul 29, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.