Method and system for improving signal integrity in integrated circuit designs
US7716621B1 · kind B1 · utility
1Cited by
5References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2005 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Dec 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of improving signal integrity in integrated circuit designs is disclosed. In some embodiments, signal integrity optimization is conducted in conjunction with detailed routing of an integrated circuit design based upon a global routing plan previously generated for the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.