Structures and methods for fabricating vertically integrated HBT-FET device

US7718486B2 · kind B2 · utility

Assignee

• ANADIGICS, INC. · US

Inventors

• Oleh Krutko · Glen Gardner, US
• Kezhou Xie · Edison, US
• Mohsen Shokrani · Haddonfield, US
• Aditya Gupta · Darsi, IN
• Boris Gedzberg · Coram, US

Key dates

• Filing date: Jan 13, 2006
• Grant date: May 18, 2010
• Expiry date: Apr 24, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/05

Abstract

Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.