Patent · US Active

Isolation structure for MOS transistor and method for forming the same

US7718506B2 · kind B2 · utility

1Cited by

6References

12Claims

0Family size

Assignee

Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

Buxin Zhang · Shanghai, CN
Yuan Wang · Beijing, CN

Key dates

Filing date	Dec 5, 2007
Grant date	May 18, 2010
Priority date	—
Expiry date	Sep 11, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0188
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.