Short pulse rejection circuit and method thereof
US7719321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Nov 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.