Active-load dominant circuit for common-mode glitch interference cancellation
US7719325B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Nov 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.