Dual-modulus prescaler circuit operating at a very high frequency
US7719326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Dec 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The dual-modulus prescaler circuit (1) is devised to operate at a very high frequency. This circuit includes an assembly formed of two dynamic D-type flip flops (12, 13), and two NAND logic gates (15, 16) arranged in negative feedback between the two flip flops. The two flip flops are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency matches the input clock frequency divided by 2 or by 3 as a function of a division mode selection signal (divb) applied to the input of the first NAND logic gate (15). One non-inverted output of the second flip flop is connected to one input of the first flip flop (12). The first dynamic flip flop includes three active branches and supplies a single inverted output signal. A third flip flop (14) with three active branches receives an inverted mode selection signal (div) at input in order to supply the mode selection signal to the inverted output thereof, clocked by the non-inverted output signal of the second flip flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.