Low-noise frequency divider
US7719327B2 · kind B2 · utility
1Cited by
6References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Feb 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/42
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider has an inverting unit and a plurality of switch inverters in series. Each switch inverter comprises two inphase switches and is controlled by a clock. The two inphase switches of each switch inverter are respectively supplied by a first voltage and a second voltage, while any two switch inverters in series are respectively controlled by two inverted clocks. The two inphase switches are selectively turned on and off synchronously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.