Configurable reset circuit for a phase-locked loop
US7719368B1 · kind B1 · utility
7Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Dec 30, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.