Crosspoint switch with low reconfiguration latency
US7719405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2004 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Aug 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power is disabled to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages. A data signal is then processed through the circuit stages in the present signal path. Before a next signal path is needed, power is re-enabled to selected disabled circuit stages in the next signal path to allow the enabled circuit stages to approach their respective enabled states. Then the next signal path can be established including the enabled circuit stages in their respective enabled states. The data signal can then be processed through the circuit stages in the next signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.