Systems and methods for ESD protection
US7719806B1 · kind B1 · utility
28Cited by
12References
70Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Oct 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/813
Abstract
A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.