FET monitoring and protecting system
US7719811B2 · kind B2 · utility
5Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A FET monitoring and protecting system (10) that includes a FET switch device (20). The FET switch device (20) includes a FET (22), a logic device (57), and a feedback status output (26). The logic device (57) is electrically coupled to the FET (22) and generates a feedback status signal. A counter (60) is incremented in response to an actual short circuit condition of the FET switch device (20). A controller (18) is electrically coupled to the feedback status output (26). The controller (18) permits the activation of the FET (22) in response to the feedback status signal and a value of the counter (60).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.