DRAM writing ahead of sensing scheme
US7719909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | May 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.