Receiver ADC clock delay base on echo signals
US7720015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2005 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jun 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.