Application of multiple voltage droop detection
US7720621B2 · kind B2 · utility
13Cited by
24References
14Claims
0Family size
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Inventor
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jun 19, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.