Fused multiply add split for multiple precision arithmetic
US7720900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Mar 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for performing floating-point operations, particularly a fused multiply add operation. The apparatus includes a arithmetic logic unit adapted to produce both a high-order part (H) and a low-order part (L) of an intermediate extended result according to H, L=A*B+C, where A, B are input operands and C an addend. Each H, L part is formatted the same as the format of the input operands, and alignment of the resulting fractions is not affected by alignment of the inputs. The apparatus includes an architecture for suppressing left-alignment of the intermediate extended result, such that input operands for a subsequent A*B+C operation remain right-aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.