System and method for exiting from an interrupt mode in a multiple processor system
US7721024B2 · kind B2 · utility
2Cited by
11References
10Claims
0Family size
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Key dates
| Filing date | Nov 12, 2003 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for interrupt processing includes a technique for exiting from interrupt mode in multiple processor systems. Those processors that were in a suspended or halt state immediately before entering the interrupt mode are released immediately with reference to the resolution of the interrupt condition. Those processors not responsible for the processing tasks associated with resolving the interrupt condition serially exit from interrupt mode on a time-delayed basis following the resolution of the interrupt condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.