Method for on-chip diagnostic testing and checking of receiver margins
US7721134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2006 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Sep 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R33/093
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.