Scheme to optimize scan chain ordering in designs
US7721171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jul 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the cir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.