ACS (add compare select) implementation for radix-4 SOVA (soft-output viterbi algorithm)
US7721187B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jul 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, an ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operative to generate the updated state metric for the state at the current trellis stage. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.