LSI circuit designing system, antenna damage preventing method and prevention controlling program used in same
US7721244B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Apr 11, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data after installation of wirings is read by layout reading processing and up-sizing candidate table is created by sizing candidate table creating processing using various libraries so that candidate values are arranged for every function cell in ascending order of gate areas. By antenna error net detecting processing, a net having wiring layers causing an antenna error is detected. A gate pin, its instance, type of a cell connected to the net is recognized by gate pin/cell recognizing processing and a cell enabling prevention of an antenna error is up-sized by cell sizing processing by referring to a gate area stored in an up-sizing candidate table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.