Printed organic logic circuits using an organic semiconductor as a resistive load device
US7723153B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Dec 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/113
Abstract
A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of an OFET to a first power supply voltage, a second portion for coupling a drain of the OFET to an output terminal and a first load resistor terminal, and a third portion for coupling a second load resistor terminal to a second power supply voltage, providing a semiconductor layer for overlapping a portion of the first and second first metal layer portions to form an OFET active area, and for overlapping a portion of the second and third metal layer portions to form a toad resistor, providing a dielectric layer for overlapping the active area of the OFET and the semiconductor area of the load resistor to isolates the first metal layer and semiconductor area from the second metal layer, and providing a second metal layer for overlapping the active area of the OFET to form a gate of the OFET and an input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.