Three dimensional integrated circuit and method of design

US7723207B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Syed M. Alam · Austin, US
• Ibrahim M. Elfadel · Laguna Niguel, US
• Kathryn Guarini · Yorktown Heights, US
• Meikei Ieong · Wappingers Falls, US
• Prabhakar Kudva · New York, US
• David S. Kung · Palo Alto, US
• Mark A. Lavin · Katonah, US
• Arifur Rahman · San Jose, US

Key dates

• Filing date: Apr 19, 2007
• Grant date: May 25, 2010
• Expiry date: May 16, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.