Stacked film patterning method and gate electrode forming method
US7723221B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | May 14, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jun 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
A stacked film patterning method is provided which is capable of reliably removing residual substances remaining after etching of a metal film, improving etching uniformity of a silicon film, and preventing an occurrence of etching residues. A micro-crystal film and a chromium film are sequentially formed on an insulating film serving as a front-end film and the chromium film is etched to be patterned by using a resist as a mask. Next, a micro-crystal silicon film on which the residual substances exist is exposed to plasma of a mixed gas including chlorine gas and oxygen gas to selectively etch the residual substances on a surface of the micro-crystal silicon film. After that, the micro-crystal silicon film is dry etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.