Lateral DMOS device structure and manufacturing method thereof
US7723780B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 2008 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | May 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A lateral DMOS device includes a body diode region and a protective diode region. The body diode region has a second conduction type well region formed in a first conduction type semiconductor substrate, the second conduction type well region including a first conduction type body region and a drain region each formed in the second conduction type well region, a first conduction type impurity region and a source region formed in the first conduction type body region, and a gate insulating film and a gate electrode formed on the first conduction type semiconductor substrate. The first conduction type body region and the second conduction type well region compose a body diode. In the protective diode region, the first conduction type impurity region is formed at a prescribed interval and the first conduction type body region and the second conduction type well region compose a protective diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.