Semiconductor wafer, semiconductor chip cut from the semiconductor wafer, and method of manufacturing semiconductor wafer
US7723826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2008 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Nov 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation film; a wiring pattern and a frame-shaped wiring dummy pattern formed on the underlying insulation film; and plural insulation films formed on the upper side of the underlying insulation film, the wiring pattern, and the wiring dummy pattern. At least one SOG film is included in the plural insulation films, in which a color pattern in accordance with a distance from the center of the semiconductor wafer based on the SOG film is formed on a surface of the insulator film within the wiring dummy pattern in top view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.