Package structure having semiconductor device embedded within wiring board
US7723838B2 · kind B2 · utility
99Cited by
10References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Apr 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.