Multilayer passive circuit topology
US7724117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2008 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jan 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/097
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.