N-channel ESD clamp with improved performance

US7724485B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Eugene R. Worley · Irvine, US
• Vivek Mohan · Everett, US
• Reza Jalilizeinali · San Diego, US

Key dates

• Filing date: Apr 20, 2007
• Grant date: May 25, 2010
• Expiry date: Jul 26, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.