Clock and power fault detection for memory modules
US7724604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2006 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Sep 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.