Patent · US Active

Method and apparatus for serial link down detection

US7724645B2 · kind B2 · utility

6Cited by

2References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Serge Bedwani · Folsom, US
Soon Seng Seh · Merang, MY
Siang Lin Tan · Bukit Mertajam, MY
Amber D. Huffman · Banks, US
Chai Huat Gan · Bukit Mertajam, MY

Key dates

Filing date	Jun 27, 2006
Grant date	May 25, 2010
Priority date	—
Expiry date	Mar 25, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/24
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.