Input/output buffer controller for optimized memory utilization and prevention of packet under-run errors
US7724756B2 · kind B2 · utility
1Cited by
2References
11Claims
0Family size
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Key dates
| Filing date | Dec 10, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jun 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9068
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To avoid under-run conditions that result in corrupt packets at I/O interfaces, a FIFO buffer controller monitors key aspects of the contents of FIFO buffers of I/O interfaces. The FIFO buffer controller initiates transmission of data from the FIFO buffer when at least one complete packet is stored in the FIFO buffer or when the size of a partial packet stored therein is large enough so that the remainder of the packet would normally be received by the FIFO buffer before the stored part can be transmitted from the FIFO buffer; thereby avoiding an under-run error condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.