Receive virtual concatenation processor
US7724781B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jan 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0094
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concatenation, contiguous concatenation as well as mixed concatenation in which some channels are contiguously concatenated and others are virtually concatenated. The processor supports virtual concatenation at both STS-1 and STS-3c granularities and with arbitrary differential delay among constituent time-slots. The processor supports contiguous concatenation with any multiple of STS-3c granularity. The processor is highly scalable to support multiple channels and different frame sizes such as STS-12, STS-48, STS-192, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.