Method and apparatus for de-jittering a clock signal
US7724812B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2006 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Dec 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0626
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a de-jittering method for a clock signal, which is implemented by adopting a controllable frequency divider and includes: taking the clock signal to be de-jittered as a reference signal, and comparing a feedback clock signal outputted by the controllable frequency divider with the reference signal; generating the control signal that is then transmitted to the controllable frequency divider; the controllable frequency divider performs frequency division upon the input high-frequency signal to generate a stable clock, and the stable clock is outputted as the feedback clock signal which has been de-jittered. The present invention also discloses a de-jittering apparatus for implementing the above-mentioned method, which includes: a circuit for generating a control signal and a controllable frequency divider. By applying the present invention, the de-jittering circuit for clock signal can be simple. What's more, transition between T1 clock frequency and E1 clock frequency can also be implemented to meet practical requirements better.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.